One difficulty with memory address and decode circuit transistors is the one time programmability of the metal oxide semiconductor field effect transistors (MOSFETs) used in such a conventional array. Another difficulty is that when floating gate transistors are used to afford in the field, or in service programmability to the array such floating gate transistors generally require high operating and high programming voltages which are not well suited to low power applications. These floating gate transistors can be EEPROM, EAPROM, and flash memory cell types. One reason for the high operating and high programming voltage requirements in these floating gate transistors is the adverse capacitance ratio between the control gate and the floating gate. In other words, the capacitance between the control gate to floating gate (CCG) is about the same as the floating gate to substrate capacitance (CFG). FIG. 1A is an illustration of a horizontal EEPROM, EAPROM, or flash memory device formed according to the teachings of the prior art. As shown in FIG. 1A, conventional horizontal floating gate transistor structures include a source region 110 and a drain region 112 separated by a channel region 106 in a horizontal substrate 100. A floating gate 104 is separated by a thin tunnel gate oxide 105 shown with a thickness (t1). A control gate 102 is separated from the floating gate 104 by an intergate dielectric 103 shown with a thickness (t2). Such conventional devices must by necessity have a control gate 102 and a floating gate 104 which are about the same size in width.
FIG. 1B is an illustration of a vertical EEPROM, EAPROM, or flash memory device formed according to the disclosure in a co-pending, commonly assigned application by W. Noble and L. Forbes, entitled "Field programmable logic array with vertical transistors," Ser. No. 09/032,617, filed Feb. 27, 1998. FIG. 1B illustrates that vertical floating gate transistor structures have a stacked source region 110 and drain region 112 separated by a vertical channel region 106. The vertical floating gate transistor shown in FIG. 1B further includes a vertical floating gate 104 separated by a thin tunnel gate oxide 105 from the channel region 106. A vertical control gate 102 is separated from the floating gate 104 by an intergate dielectric 103. As shown in FIG. 1B, the vertical control gate 102 and the vertical floating gate 104 are likewise about the same size in width relative to the channel region 106.
Conventionally, the insulator, or intergate dielectric, 103 between the control gate 102 and the floating gate 104 is thicker (t2) than the gate oxide 105 (t1) to avoid tunnel current between the gates. The insulator, or intergate dielectric, 103 is also generally made of a higher dielectric constant insulator 103, such as silicon nitride or silicon oxynitride. This greater insulator thickness (t2) tends to reduce capacitance. The higher dielectric constant insulator 103, on the other hand, increases capacitance. As shown in FIG. 1C, the net result is that the capacitance between the control gate and the floating gate (CCG) is about the same as the gate capacitance of the thinner gate tunneling oxide 105 between the floating gate and the substrate (CFG). This undesirably results in large control gate voltages being required for tunneling, since the floating gate potential will be only about one half that applied to the control gate.
As design rules and feature size (F) in floating gate transistors continue to shrink, the available chip surface space in which to fabricate the floating gate also is reduced. In order to achieve a higher capacitance between the control gate and floating gate (CCG) some devices have used even higher dielectric constant insulators between the control gate and floating gate. Unfortunately, using such higher dielectric constant insulators involves added costs and complexity to the fabrication process.
Therefore, there is a need in the art to provide field programmable memory address and decode circuits which can operate with lower control gate voltages and which do not increase the costs or complexity of the fabrication process. Further such devices should desirably be able to scale with shrinking design rules and feature sizes in order to provide even higher density integrated circuits.